64 lines
2.3 KiB
Plaintext
64 lines
2.3 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {type=subcircuit
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vhdl_stop=true
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verilog_netlist=true
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format="@name @pinlist @symname"
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template="name=x1 dim=5 width=8 hex=0
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datafile=ram.list modulename=ram access_delay=3000 oe_delay=300"
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generic_type="datafile=string modulename=string"
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}
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V {}
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S {}
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E {}
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L 4 -130 -70 130 -70 {}
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L 4 -130 70 130 70 {}
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L 4 -130 -70 -130 70 {}
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L 4 130 -70 130 70 {}
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L 4 -150 -60 -130 -60 {}
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L 4 -150 -40 -130 -40 {}
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L 4 130 -60 150 -60 {}
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L 4 -150 -20 -130 -20 {}
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L 4 -150 0 -130 0 {}
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L 4 -150 20 -130 20 {}
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L 4 -150 40 -130 40 {}
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L 4 -150 60 -130 60 {}
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B 5 -152.5 57.5 -147.5 62.5 {name=CK dir=in sim_pinnumber=1}
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B 5 -152.5 37.5 -147.5 42.5 {name=OEN dir=in sim_pinnumber=2}
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B 5 -152.5 17.5 -147.5 22.5 {name=CEN dir=in sim_pinnumber=3}
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B 5 -152.5 -2.5 -147.5 2.5 {name=WEN dir=in sim_pinnumber=4}
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B 5 -152.5 -22.5 -147.5 -17.5 {name=DIN[width-1:0] dir=in sim_pinnumber=5}
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B 5 -152.5 -42.5 -147.5 -37.5 {name=M[width-1:0] dir=in sim_pinnumber=6}
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B 5 -152.5 -62.5 -147.5 -57.5 {name=ADD[dim-1:0] dir=in sim_pinnumber=7}
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B 5 147.5 -62.5 152.5 -57.5 {name=DOUT[width-1:0] verilog_type=wire dir=out sim_pinnumber=8 }
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T {@symname} -31.5 -6 0 0 0.3 0.3 {}
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T {@name} 135 -82 0 0 0.2 0.2 {}
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T {ADD[dim-1:0]} -125 -64 0 0 0.2 0.2 {}
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T {M[width-1:0]} -125 -44 0 0 0.2 0.2 {}
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T {DOUT[width-1:0]} 125 -64 0 1 0.2 0.2 {}
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T {DIN[width-1:0]} -125 -24 0 0 0.2 0.2 {}
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T {WEN} -125 -4 0 0 0.2 0.2 {}
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T {CEN} -125 16 0 0 0.2 0.2 {}
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T {OEN} -125 36 0 0 0.2 0.2 {}
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T {CK} -125 56 0 0 0.2 0.2 {}
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