52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=subcircuit
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @symname"
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template="name=x1 delay=\\"200 ps\\" del=200"
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generic_type="delay=time"}
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V {}
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S {}
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E {}
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L 4 -50 -30 50 -30 {}
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L 4 -50 30 50 30 {}
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L 4 -50 -30 -50 30 {}
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L 4 50 -30 50 30 {}
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L 4 -70 -20 -50 -20 {}
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L 4 50 -20 70 -20 {}
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L 4 -70 20 -50 20 {}
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L 4 0 30 0 50 {}
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L 4 50 20 70 20 {}
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B 5 -72.5 -22.5 -67.5 -17.5 {name=D dir=in}
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B 5 67.5 -22.5 72.5 -17.5 {name=Q dir=out}
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B 5 -72.5 17.5 -67.5 22.5 {name=G dir=in}
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B 5 -2.5 47.5 2.5 52.5 {name=RST dir=in}
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B 5 67.5 17.5 72.5 22.5 {name=QN dir=out}
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T {@symname} -32.5 -6 0 0 0.3 0.3 {}
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T {@name} 55 -42 0 0 0.2 0.2 {}
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T {D} -45 -24 0 0 0.2 0.2 {}
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T {Q} 45 -24 0 1 0.2 0.2 {}
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T {G} -45 16 0 0 0.2 0.2 {}
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T {RST} -10 16 0 0 0.2 0.2 {}
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T {QN} 45 16 0 1 0.2 0.2 {}
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