391 lines
11 KiB
XML
391 lines
11 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {}
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K {}
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V {
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}
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S {
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.param VCC=2
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vaa3 aa[3] 0 dc 0
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vaa2 aa[2] 0 dc 0
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vaa1 aa[1] 0 dc 0
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vaa0 aa[0] 0 dc 0
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vbb bb 0 dc 0
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vcckk cckk 0 dc 0
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vrrsstt rrsstt 0 dc 0
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.op
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}
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E {}
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T {Netlister allows duplicated pins on symbols
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Electrical nodes are propagated through duplicated symbol pins} 50 -1570 0 0 1 1 {}
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N 480 -930 630 -930 {
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lab=RRSSTT}
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N 480 -910 630 -910 {
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lab=CCKK}
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N 480 -890 630 -890 {
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lab=AA[3:0]}
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N 480 -870 630 -870 {
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lab=BB}
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N 480 -830 510 -830 {
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lab=ZZ[5]}
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N 930 -830 960 -830 {
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lab=ZZ[6]}
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N 480 -1060 510 -1060 {
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lab=ZZ[3]}
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N 930 -1060 960 -1060 {
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lab=ZZ[4]}
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N 480 -1290 510 -1290 {
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lab=ZZ[1]}
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N 930 -1290 960 -1290 {
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lab=ZZ[2]}
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N 480 -1390 630 -1390 {
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lab=RRSSTT}
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N 480 -1370 630 -1370 {
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lab=CCKK}
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N 480 -1350 630 -1350 {
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lab=AA[3:0]}
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N 480 -1330 630 -1330 {
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lab=BB}
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N 480 -720 660 -720 {
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lab=RRSSTT}
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N 480 -700 660 -700 {
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lab=CCKK}
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N 480 -680 660 -680 {
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lab=AA[3:0]}
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N 480 -660 660 -660 {
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lab=BB}
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N 480 -620 510 -620 {
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lab=ZZ[7]}
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N 630 -620 660 -620 {
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lab=ZZ[8]}
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N 960 -720 1080 -720 {
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lab=RRSSTT}
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N 960 -700 1080 -700 {
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lab=CCKK}
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N 960 -680 1080 -680 {
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lab=AA[3:0]}
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N 960 -660 1080 -660 {
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lab=BB}
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N 1380 -620 1410 -620 {
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lab=ZZ[9]}
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N 410 -510 660 -510 {
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lab=#net1}
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N 410 -490 660 -490 {
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lab=#net2}
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N 410 -470 660 -470 {
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lab=#net3}
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N 410 -450 660 -450 {
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lab=#net4}
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N 410 -410 440 -410 {
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lab=ZZ[12]}
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N 630 -410 660 -410 {
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lab=ZZ[11]}
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N 1260 -410 1290 -410 {
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lab=ZZ[10]}
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N 1520 -990 1550 -990 {
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lab=ZZ[13]}
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N 1170 -1090 1220 -1090 {
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lab=RRSSTT}
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N 1170 -1070 1220 -1070 {
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lab=CCKK}
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N 1170 -1050 1220 -1050 {
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lab=AA[3:0]}
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N 1170 -1030 1220 -1030 {
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lab=BB}
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N 1190 -1250 1220 -1250 {
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lab=ZZ[14]}
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N 1170 -1350 1220 -1350 {
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lab=RRSSTT}
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N 1170 -1330 1220 -1330 {
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lab=CCKK}
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N 1170 -1310 1220 -1310 {
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lab=AA[3:0]}
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N 1170 -1290 1220 -1290 {
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lab=BB}
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N 670 -280 710 -280 {
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lab=#net5}
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N 480 -260 710 -260 {
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lab=#net6}
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N 480 -240 710 -240 {
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lab=#net7}
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N 480 -220 710 -220 {
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lab=#net8}
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N 480 -180 510 -180 {
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lab=ZZ[17]}
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N 680 -180 710 -180 {
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lab=ZZ[16]}
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N 1010 -280 1080 -280 {
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lab=#net5}
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N 1010 -260 1080 -260 {
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lab=#net6}
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N 1010 -240 1080 -240 {
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lab=#net7}
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N 1010 -220 1080 -220 {
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lab=#net8}
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N 1380 -180 1410 -180 {
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lab=ZZ[15]}
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N 10 -260 40 -260 {
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lab=#net9}
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N 120 -260 180 -260 {
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lab=#net6}
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N 0 -450 30 -450 {
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lab=#net10}
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N 1260 -510 1440 -510 {
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lab=#net1}
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N 1260 -490 1440 -490 {
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lab=#net2}
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N 1260 -470 1440 -470 {
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lab=#net3}
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N 1260 -450 1440 -450 {
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lab=#net4}
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N 1740 -310 1770 -310 {
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lab=ZZ[18]}
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N 1740 -410 1740 -310 {
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lab=ZZ[18]}
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N 2040 -310 2070 -310 {
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lab=ZZ[19]}
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N 2040 -410 2040 -310 {
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lab=ZZ[19]}
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N 670 -350 670 -280 {
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lab=#net5}
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N 670 -350 730 -350 {
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lab=#net5}
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N 810 -350 860 -350 {
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lab=#net11}
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N 1110 -920 1260 -920 {
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lab=RRSSTT}
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N 1110 -900 1260 -900 {
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lab=CCKK}
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N 1110 -880 1260 -880 {
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lab=AA[3:0]}
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N 1110 -860 1260 -860 {
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lab=BB}
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N 1560 -820 1590 -820 {
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lab=ZZ[20]}
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N 1690 -920 1760 -920 {
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lab=RRSSTT}
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N 1560 -900 1760 -900 {
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lab=CCKK}
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N 1560 -880 1760 -880 {
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lab=AA[3:0]}
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N 1730 -860 1760 -860 {
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lab=BB}
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N 1730 -820 1760 -820 {
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lab=ZZ[21]}
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N 2060 -880 2080 -880 {
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lab=AA[3:0]}
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N 2060 -860 2080 -860 {
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lab=BB}
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N 2060 -900 2080 -900 {
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lab=CCKK}
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N 2060 -920 2080 -920 {
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lab=RRSSTT}
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N 1690 -1070 1690 -920 {
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lab=RRSSTT}
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N 1690 -1370 1820 -1370 {
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lab=RRSSTT}
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N 1730 -1110 1730 -860 {
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lab=BB}
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N 1730 -1410 1820 -1410 {
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lab=BB}
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N 1980 -1330 2060 -1330 {
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lab=BB}
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N 2220 -1330 2280 -1330 {
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lab=RRSSTT}
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N 2220 -1250 2280 -1250 {
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lab=BB}
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N 2260 -1030 2360 -1030 {
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lab=BB}
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N 2260 -950 2300 -950 {
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lab=RRSSTT}
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N 1730 -1110 1780 -1110 {
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lab=BB}
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N 1690 -1070 1780 -1070 {
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lab=RRSSTT}
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N 2330 -930 2360 -930 {
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lab=ZZ[22]}
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N 2660 -990 2690 -990 {
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lab=#net12}
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N 2660 -970 2690 -970 {
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lab=RRSSTT}
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N 2660 -1010 2690 -1010 {
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lab=#net13}
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N 2660 -1030 2690 -1030 {
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lab=BB}
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N 2300 -970 2300 -950 {
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lab=RRSSTT}
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N 2300 -970 2360 -970 {
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lab=RRSSTT}
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N 480 -280 670 -280 {
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lab=#net5}
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N 1560 -920 1690 -920 {
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lab=RRSSTT}
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N 1560 -860 1730 -860 {
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lab=BB}
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N 1730 -1410 1730 -1110 {
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lab=BB}
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N 2300 -1010 2360 -1010 {
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lab=#net13}
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N 2300 -990 2360 -990 {
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lab=#net12}
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N 1690 -1370 1690 -1070 {
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lab=RRSSTT}
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N 1980 -1290 2060 -1290 {
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lab=RRSSTT}
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N 2220 -1290 2280 -1290 {
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lab=BB}
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N 2220 -1210 2280 -1210 {
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lab=RRSSTT}
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N 2140 -1410 2200 -1410 {
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lab=BB}
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N 2140 -1370 2200 -1370 {
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lab=RRSSTT}
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N 1920 -1490 1980 -1490 {
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lab=BB}
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N 1920 -1450 1980 -1450 {
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lab=RRSSTT}
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C {doublepin.sym} 1230 -670 0 0 {name=x9
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}
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C {doublepin.sym} 810 -670 0 1 {name=x8
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}
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C {doublepin.sym} 780 -880 0 0 {name=x2
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}
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C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ[5]}
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C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ[6]}
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C {lab_wire.sym} 550 -930 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
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C {lab_wire.sym} 550 -910 0 0 {name=l4 sig_type=std_logic lab=CCKK}
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C {lab_wire.sym} 550 -870 0 0 {name=l5 sig_type=std_logic lab=BB}
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C {doublepin.sym} 330 -1110 0 0 {name=x3
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}
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C {doublepin.sym} 780 -1110 0 0 {name=x4
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}
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C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ[3]}
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C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ[4]}
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C {lab_pin.sym} 180 -1160 0 0 {name=l7 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 180 -1140 0 0 {name=l8 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 180 -1100 0 0 {name=l9 sig_type=std_logic lab=BB}
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C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 930 -1160 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 930 -1140 0 1 {name=l12 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 930 -1100 0 1 {name=l13 sig_type=std_logic lab=BB}
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C {doublepin.sym} 330 -1340 0 0 {name=x5
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}
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C {doublepin.sym} 780 -1340 0 0 {name=x6
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}
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C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ[1]}
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C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ[2]}
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C {lab_pin.sym} 180 -1390 0 0 {name=l15 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 180 -1370 0 0 {name=l16 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 180 -1330 0 0 {name=l17 sig_type=std_logic lab=BB}
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C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 930 -1390 0 1 {name=l19 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 930 -1370 0 1 {name=l20 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 930 -1330 0 1 {name=l21 sig_type=std_logic lab=BB}
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C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA[3:0]}
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C {lab_wire.sym} 550 -1390 0 0 {name=l23 sig_type=std_logic lab=RRSSTT}
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C {lab_wire.sym} 550 -1370 0 0 {name=l24 sig_type=std_logic lab=CCKK}
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C {lab_wire.sym} 550 -1330 0 0 {name=l25 sig_type=std_logic lab=BB}
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C {lab_pin.sym} 180 -660 0 0 {name=l33 sig_type=std_logic lab=BB}
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C {doublepin.sym} 330 -880 0 0 {name=x1
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}
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C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ[7]}
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C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ[8]}
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C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK}
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C {doublepin.sym} 330 -670 0 0 {name=x7
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}
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C {iopin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT }
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C {iopin.sym} 100 -100 0 0 { name=p10 lab=CCKK }
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C {iopin.sym} 100 -120 0 0 { name=p11 lab=BB }
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C {iopin.sym} 100 -140 0 0 { name=p12 lab=AA[3:0] }
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C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[22:1]}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ[9]}
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C {doublepin.sym} 1110 -460 0 0 {name=x10
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}
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C {doublepin.sym} 810 -460 0 1 {name=x11
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}
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C {lab_pin.sym} 440 -410 0 1 {name=p7 lab=ZZ[12]}
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C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ[11]}
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C {doublepin.sym} 260 -460 0 0 {name=x12
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}
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C {lab_pin.sym} 1290 -410 0 1 {name=p1 lab=ZZ[10]}
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C {doublepin.sym} 1370 -1040 0 0 {name=x13
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}
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C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ[13]}
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C {lab_pin.sym} 1520 -1050 0 1 {name=l1 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 1520 -1090 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 1520 -1070 0 1 {name=l12 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 1520 -1030 0 1 {name=l13 sig_type=std_logic lab=BB}
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C {doublepin.sym} 1370 -1300 0 1 {name=x14
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}
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C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ[14]}
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C {lab_pin.sym} 1520 -1310 0 1 {name=l3 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 1520 -1350 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
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C {lab_pin.sym} 1520 -1330 0 1 {name=l12 sig_type=std_logic lab=CCKK}
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C {lab_pin.sym} 1520 -1290 0 1 {name=l13 sig_type=std_logic lab=BB}
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C {doublepin.sym} 330 -230 0 0 {name=x17[1:0]
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}
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C {doublepin.sym} 860 -230 0 1 {name=x16[1:0]
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}
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C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ[17]}
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C {lab_pin.sym} 680 -180 0 0 {name=p8 lab=ZZ[16]}
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C {doublepin.sym} 1230 -230 0 0 {name=x22[1:0]
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}
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C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ[15]}
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C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000}
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C {inv_ngspice.sym} 70 -450 0 0 {name=x19 ROUT=1000}
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C {doublepin.sym} 1590 -460 0 0 {name=x20
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}
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C {lab_pin.sym} 1770 -310 0 1 {name=p8 lab=ZZ[18]}
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C {doublepin.sym} 1890 -460 0 0 {name=x21
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}
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C {lab_pin.sym} 2070 -310 0 1 {name=p8 lab=ZZ[19]}
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C {inv_ngspice.sym} 770 -350 0 0 {name=x15 ROUT=1000}
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C {doublepin.sym} 1410 -870 0 0 {name=x23
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}
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C {lab_wire.sym} 1180 -880 0 0 {name=l2 sig_type=std_logic lab=AA[3:0]}
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C {lab_pin.sym} 1590 -820 0 1 {name=p5 lab=ZZ[20]}
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C {lab_wire.sym} 1180 -920 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
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C {lab_wire.sym} 1180 -900 0 0 {name=l4 sig_type=std_logic lab=CCKK}
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C {lab_wire.sym} 1180 -860 0 0 {name=l5 sig_type=std_logic lab=BB}
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C {doublepin.sym} 1910 -870 0 1 {name=x24
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}
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C {lab_pin.sym} 1730 -820 0 0 {name=p5 lab=ZZ[21]}
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C {xcross.sym} 1900 -1370 0 0 {name=x25}
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C {xcross.sym} 2140 -1290 0 0 {name=x26}
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C {xcross.sym} 1860 -1070 0 0 {name=x27}
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C {xcross.sym} 2020 -1070 0 0 {name=x28}
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C {xcross.sym} 2180 -990 0 0 {name=x29}
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C {doublepin.sym} 2510 -980 0 1 {name=x30
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}
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C {lab_pin.sym} 2330 -930 0 0 {name=p5 lab=ZZ[22]}
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C {xcross.sym} 2060 -1410 2 0 {name=x31}
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C {use.sym} 1590 -100 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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