66 lines
1.6 KiB
XML
66 lines
1.6 KiB
XML
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {
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process
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variable buf: LINE;
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variable last : time;
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variable val : real;
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begin
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if now = 0 ns then
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last := now;
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USC.cap <=cap;
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USC.conduct <=0.0;
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USC.value <= 0.0;
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end if;
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wait on USC until last /=now;
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last := now;
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WRITE(buf,string'("start real_capa process"));
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WRITELINE(output,buf);
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USC.conduct <= 0.0;
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USC.cap <= cap ;
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val := USC.value'LAST_VALUE;
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if now = 0 ns then
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USC.value <= 0.0;
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else
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USC.value <= val;
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end if;
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end process;
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}
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K {}
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V {}
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S {}
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E {}
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C {iopin.sym} 50 -80 0 0 {name=p1 lab=USC sig_type=rreal}
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C {use.sym} -120 -340 0 0 {library ieee;
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use std.TEXTIO.all;
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use ieee.std_logic_1164.all;
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library work;
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use work.rrreal_pkg.all;
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}
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