47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2024 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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G {type=subcircuit
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format="@name @pinlist @symname VTH=@VTH VHI=@VHI"
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template="name=x1 VTH=1.5 VHI=3.0"
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}
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V {}
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S {}
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E {}
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L 4 -70 -20 70 -20 {}
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L 4 -70 40 70 40 {}
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L 4 -70 -20 -70 40 {}
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L 4 70 -20 70 40 {}
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L 4 -90 -10 -70 -10 {}
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L 4 70 -10 90 -10 {}
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L 4 -90 10 -70 10 {}
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L 4 -90 30 -70 30 {}
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B 5 -92.5 -12.5 -87.5 -7.5 {name=D dir=in }
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B 5 87.5 -12.5 92.5 -7.5 {name=Q dir=out }
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B 5 -92.5 7.5 -87.5 12.5 {name=G dir=in }
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B 5 -92.5 27.5 -87.5 32.5 {name=VSS dir=in }
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T {@symname} -31.5 -6 0 0 0.3 0.3 {}
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T {@name} 75 -32 0 0 0.2 0.2 {}
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T {D} -65 -14 0 0 0.2 0.2 {}
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T {Q} 65 -14 0 1 0.2 0.2 {}
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T {G} -65 6 0 0 0.2 0.2 {}
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T {VSS} -65 26 0 0 0.2 0.2 {}
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