A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Go to file

Chayan Deb 937e8b2f7b [Resolved Merge Conflicts]: All upstream updates to the codebase has been integrated into the fork.		2025-03-11 11:12:25 +05:30
.github/workflows	Configure github CI	2023-05-06 02:04:30 +02:00
XSchemWin	eval_expr.y: fix eval_expr_clear_table, remove unneeded unistd.h	2025-02-14 02:15:03 +01:00
doc	add command `xschem raw rename old_node new_node`	2025-03-08 21:14:46 +01:00
scconfig	fix some c89 violations (warnings)	2025-01-10 16:14:24 +01:00
src	[Resolved Merge Conflicts]: All upstream updates to the codebase has been integrated into the fork.	2025-03-11 11:12:25 +05:30
tests	allow `xschem translate -1 string` to translate tokens that do not depend on specific instances; yet another change in wrap detection in graphs, always use simulator sweep-var instead of user specified sweep variable; simulated data will never wrap exactly to first value due to roundoff errors; -fast optionto `xschem hilight_netname` command	2025-01-24 03:52:20 +01:00
xschem_library	revert res.sym	2025-03-04 10:01:29 +01:00
.gitignore	[Refactor]: Manually added the refactoring changes introduced into upstream repository.	2025-02-19 17:00:34 +05:30
AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
CMakeLists.txt	Added png and embedded graphs to ps and pdf export	2023-01-15 21:34:43 -07:00
Changelog	update Changelog	2024-12-16 17:01:38 +01:00
INSTALL	populating xschem git repo	2020-08-08 15:47:34 +02:00
LICENSE	update license info	2021-07-27 16:42:54 +02:00
Makefile	make uninstall: remove empty directories (share/xschem and share/doc/xschem); make command `xschem help` work also if running in src/ directory; use XSCHEM_SHAREDIR shell variable (if defined and directory existing), else set XCSCHEM_SHAREDIR to `pwd` if started from src/ dir, else set compile set XSCHEM_SHAREDIR. xschemrc can override this XSCHEM_SHAREDIR setting.	2025-01-05 01:29:04 +01:00
Makefile.conf.in	remove check for libreadline (not used)	2024-11-13 01:35:24 +01:00
README	update license info	2021-07-27 16:42:54 +02:00
README.md	Update README.md	2020-10-08 00:54:06 +02:00
README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	remove check for libreadline (not used)	2024-11-13 01:35:24 +01:00
configure	populating xschem git repo	2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions