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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 910235749b small updates to solar_panel.sch test schematic 2023-06-12 08:17:42 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin added command `xschem getprop instance_notcl` to avoid tcl subst of the resulting attribute; improved fix_symbols to fix also parametrized generators (pcells) 2023-06-08 23:02:40 +02:00
doc improve `Shift-M` command by stretching nets that land on instance pins while moving instances 2023-06-10 23:41:02 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src drill_hilight(): propagate unnamed nets connected to multiple instances (R1[3:0]), do not try to get single bits out of unnamed nets, as the whole netname is hashed 2023-06-12 07:25:05 +02:00
tests update hash of greycnt.v in xschemtest.tcl due to comments lines added in netlist for bus taps 2023-06-08 11:01:34 +02:00
xschem_library small updates to solar_panel.sch test schematic 2023-06-12 08:17:42 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions