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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
855 Commits 3 Branches 10 Tags 86 MiB
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Tcl 15.8%
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Stefan Frederik 8cc6315e09 graphical improvements for better graph scaling 2021-12-29 06:21:51 +01:00
XSchemWin fix BadDrawable regression in free_rawfile(): after deleting data a draw() was called, but since this function is called also in exit handler all windows are already closed. Added digital waveforms and bussed signal display 2021-12-29 05:11:39 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
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tests added typedefs on used structs, updated xschemtest with new hashes 2021-12-28 01:33:01 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions