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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 89d90c21db xctx->sch made an array of pointers instead of array of PATH_MAX strings (memory saver) 2023-06-17 23:58:35 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin separated @#pin:attr handling in translate() into *get_pin_attr(), replaced sscanf() with dedicated get_pin_and_attr() so we are able to handle stuff like "@#ADD[7:0]:net_name" 2023-06-16 10:55:22 +02:00
doc show red dot when cuting a wire with new alt-right button click on a wire. Added also menu command in Tools 2023-06-14 10:08:50 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src xctx->sch made an array of pointers instead of array of PATH_MAX strings (memory saver) 2023-06-17 23:58:35 +02:00
tests update spice netlist hash for inst_sch_select.sch in xschemtest.tcl 2023-06-13 23:20:28 +02:00
xschem_library fix memory leak due to improper use of get_pin_and_attr() 2023-06-17 10:14:55 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update copyright info to 2023 2023-05-21 12:52:19 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions