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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
319 Commits 3 Branches 10 Tags 86 MiB
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Stefan Frederik 7da61bc054 draw wide lines (bus=true attribute) in svg export 2020-11-30 23:20:06 +01:00
XSchemWin added some comments 2020-11-26 04:01:11 +01:00
doc removed event_reporting feature 2020-11-29 03:27:45 +01:00
scconfig added some comments 2020-11-26 04:01:11 +01:00
src draw wide lines (bus=true attribute) in svg export 2020-11-30 23:20:06 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library allow new lines in net names (!) 2020-11-30 22:12:31 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions