A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Go to file

stefan schippers 78fdab27fc fix typo in "".menubar entryconfigure Simulate -background" in actions.c:set_modify()		2025-09-02 21:31:08 +02:00
.github/workflows	…
XSchemWin	…
doc	doc updates (spectre global=ground specificaton for net names)	2025-08-27 00:15:05 +02:00
scconfig	…
src	fix typo in "".menubar entryconfigure Simulate -background" in actions.c:set_modify()	2025-09-02 21:31:08 +02:00
tests	vector unnamed nets are set as net%d_[%d..0] instead of net%d[%d:0] so they are compatible with spice and Vacask	2025-08-03 00:15:57 +02:00
xschem_library	update filesource.sym (no need to specify model, generated automatically from @name)	2025-09-01 11:59:35 +02:00
.gitignore	…
AUTHORS	…
CMakeLists.txt	…
Changelog	…
INSTALL	…
LICENSE	…
Makefile	…
Makefile.conf.in	…
README	…
README.md	…
README_MacOS.md	…
config.h.in	…
configure	…

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions