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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Chayan Deb 76e106563b [UI/UX Enhancement]: When the 'w'-key is pressed to enter wire-drawing mode, until drawing begins with an LMB-click - a new bottom status-bar entry will appear in deep blue color along with the text {WIRE READY TO DRAW! } - indicating the current editor mode. Either pressing 'Esc'-key, or starting the wire-drawing process with an LMB-click will cause this new status-bar entry to disappear. 2025-01-02 18:46:46 +05:30
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin updated greycnt.sch example 2024-12-18 14:01:50 +01:00
doc update keys.help 2024-12-29 21:37:17 +01:00
scconfig xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
src [UI/UX Enhancement]: When the 'w'-key is pressed to enter wire-drawing mode, until drawing begins with an LMB-click - a new bottom status-bar entry will appear in deep blue color along with the text {WIRE READY TO DRAW! } - indicating the current editor mode. Either pressing 'Esc'-key, or starting the wire-drawing process with an LMB-click will cause this new status-bar entry to disappear. 2025-01-02 18:46:46 +05:30
tests update xschemtest expected netlist hashes 2024-12-23 11:15:36 +01:00
xschem_library code comments 2024-12-23 12:24:06 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog 2024-12-16 17:01:38 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions