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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 75db846e58 ask confirmation if pressing "s" for simulate; node lists in graph dialog box are returned as they are with no tcleval() resolution; poweramp.sch now can be simulated unchanged with Xyce 2022-09-13 00:31:20 +02:00
XSchemWin add xschem get zoom to query zoom factor 2022-08-24 11:22:26 +02:00
doc sys-lib-path: add /devices in configure log shown text 2022-08-13 11:02:18 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src ask confirmation if pressing "s" for simulate; node lists in graph dialog box are returned as they are with no tcleval() resolution; poweramp.sch now can be simulated unchanged with Xyce 2022-09-13 00:31:20 +02:00
tests inst_hash_lookup() will insert and lookup only instance basename (x1[3:0] --> x1) so better and stronger uniquenes of instance names is ensured. ngspice_backannotate accepts a filename (if not given assume as before <circuit_name>.raw) 2022-09-12 12:01:26 +02:00
xschem_library ask confirmation if pressing "s" for simulate; node lists in graph dialog box are returned as they are with no tcleval() resolution; poweramp.sch now can be simulated unchanged with Xyce 2022-09-13 00:31:20 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions