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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
285 Commits 3 Branches 10 Tags 91 MiB
C 71.4%
Tcl 15.9%
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Stefan Schippers 759c44078e optimization: avoid calling get_tok_value in storeobject() if no attributes are given 2020-11-19 16:48:44 +01:00
XSchemWin Fixed Windows Xschem running from VS2019 without installing Xschem to find (Root)/xschem_library/devices as XSCHEM_LIBRARY_PATH, so that viewing schematics through VS2019 will find all symbols in xschem_library/devices. Moved doc and xschem_library XML files to its own *.wxs. Cleaned up Product.wxs by taking out doc and xschem_library files; fixed spacings in License.rtf; added condition that proper version of Active TCL is required to install 2020-11-07 10:52:50 +01:00
doc "Delete files" menu command added 2020-10-24 23:46:19 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src optimization: avoid calling get_tok_value in storeobject() if no attributes are given 2020-11-19 16:48:44 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library reduce svg size by avoiding redundant attributes in elements, fix a regression in scheduler.c (missing else clause) 2020-11-18 23:20:50 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog Changelog update 2020-11-19 15:57:53 +01:00
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README.md Update README.md 2020-10-08 00:54:06 +02:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions