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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Merge branch 'StefanSchippers:master' into master 		2025-01-02 18:55:36 +05:30
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XSchemWin updated greycnt.sch example 2024-12-18 14:01:50 +01:00
doc load_schematic(): do not set xctx->time_last_modify if called with reset_undo == 0; fix persistent command mode when started from menu; update traversal procedures 2025-01-02 12:52:51 +01:00
scconfig xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions