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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 6c1dadd27c flush unused symbols at end of netlist 2023-12-02 23:25:54 +01:00
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XSchemWin fix occasional crashes due to graph_fullxzoom() getting sweep variable index in raw file before switching to graph-specific raw file 2023-11-29 01:26:45 +01:00
doc attribute default_schematic=ignore: if set in a symbol xschem will not descend into the default schematic associated to symbol. Instances MUST specify a schematic attribute 2023-12-02 13:17:32 +01:00
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tests break.awk: do not break user code lines in spice netlists 2023-12-02 23:00:44 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions