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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
110 Commits 3 Branches 10 Tags 87 MiB
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Tcl 15.7%
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Stefan Schippers 66a8eabf7e fix un-graceful termination of load_sym_def() in case of recursive schematics instantiating themselves. It was not allowed to unroll all hierarchy levels cleaning up allocated memory after issuing the max-hierarchy warning. 2020-09-24 15:59:01 +02:00
XSchemWin Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
doc add attributes "weight=bold", "slant=italic", "slant=oblique" on text objects for bold/italic/oblique texts, doc updates. 2020-09-23 18:15:26 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src fix un-graceful termination of load_sym_def() in case of recursive schematics instantiating themselves. It was not allowed to unroll all hierarchy levels cleaning up allocated memory after issuing the max-hierarchy warning. 2020-09-24 15:59:01 +02:00
tests Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port. 2020-08-10 23:43:20 +02:00
xschem_library apply visible layers (View->Symbol visible layers) to any object (lines. arcs, text etc),better bounding box calculation for slant text 2020-09-23 22:13:39 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog fix Browse button in edit symbol prop dialog 2020-09-15 14:15:43 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE added LICENSE 2020-08-09 09:12:07 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Add manual link 2020-08-08 16:04:20 +02:00
config.h.in populating xschem git repo 2020-08-08 15:47:34 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html