A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 582863f825 added menu option to load most recent file: ctrl-shift-o, fix menu entry "unhilight selected nets" (did unhilight all); removed a wire[].node clear in hash_wire() that caused broken connectivity. this data is cleared in delete_netlist_structs when needed. 2020-12-25 04:37:53 +01:00
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src added menu option to load most recent file: ctrl-shift-o, fix menu entry "unhilight selected nets" (did unhilight all); removed a wire[].node clear in hash_wire() that caused broken connectivity. this data is cleared in delete_netlist_structs when needed. 2020-12-25 04:37:53 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library added menu option to load most recent file: ctrl-shift-o, fix menu entry "unhilight selected nets" (did unhilight all); removed a wire[].node clear in hash_wire() that caused broken connectivity. this data is cleared in delete_netlist_structs when needed. 2020-12-25 04:37:53 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions