A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Frederik 57fb2c7c0f doc updates for F-SiC 2022 conf		2022-06-09 15:17:59 +02:00
XSchemWin	Correct background color for monochrome svg exports, close stdin if xschem started with -b to avoid blocking when spawning ngspice batch tasks	2022-05-12 23:32:57 +02:00
doc	doc updates for F-SiC 2022 conf	2022-06-09 15:17:59 +02:00
scconfig	more conversion warnings suppressed	2022-04-28 10:12:16 +02:00
src	when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)	2022-06-09 09:32:34 +02:00
tests	update xschemtest.tcl to reflect new verilog 2001 syntax for params	2022-04-25 11:30:23 +02:00
xschem_library	when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)	2022-06-09 09:32:34 +02:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
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Changelog	bump version to 3.0.0; prepare for 3.0.0 release	2021-09-11 07:53:11 +02:00
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README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables	2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions