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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 53dc7fe3bf add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model. 2022-09-19 11:22:04 +02:00
XSchemWin fix a crash due to reentrant call of preview schematic drawing caused by an Expose event if an alert box is displayed due to errors in schematic to preview 2022-09-17 11:27:42 +02:00
doc do not show bboxes of hidden texts while moving objects if global option "show hidden texts" is not set; documentation updates 2022-09-16 13:19:26 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model. 2022-09-19 11:22:04 +02:00
tests various small fixes for cursor b backannotation, updated xschemtest netlist hashes 2022-09-18 12:25:09 +02:00
xschem_library add backannotation info (as hidden text) in lab_pin.sym, lab_wire.sym, transitioning example schematics from old (push) backannotation model to new pull model. 2022-09-19 11:22:04 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions