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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 5338deac78 add erc_open_net_is_error and erc_shorted_output_is_error xschemrc variables to turn related ERC warnings into errors (force popup ERC window) 2025-08-23 00:35:27 +02:00
.github/workflows Update ci.yaml 2025-05-07 16:16:25 +02:00
XSchemWin print_spice_element(): do not substitute "extra" pins in format string (like @body) with body=xxx given in parent symbol instance attributes 2025-05-20 02:51:52 +02:00
doc ctrl-Tab: toggle to previously active tab (only tabbed i/f) 2025-08-22 12:09:04 +02:00
scconfig prepare for 3.4.7 tag 2025-05-14 09:58:55 +02:00
src add erc_open_net_is_error and erc_shorted_output_is_error xschemrc variables to turn related ERC warnings into errors (force popup ERC window) 2025-08-23 00:35:27 +02:00
tests vector unnamed nets are set as net%d_[%d..0] instead of net%d[%d:0] so they are compatible with spice and Vacask 2025-08-03 00:15:57 +02:00
xschem_library update bindkeys_cheatsheet.sym (prev/next tab commands, arrow keys) 2025-08-22 00:18:37 +02:00
.gitignore added eval_expr.c to .gitignore 2025-02-10 23:36:21 +01:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog prepare for 3.4.7 tag 2025-05-14 09:58:55 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile make uninstall: remove empty directories (share/xschem and share/doc/xschem); make command `xschem help` work also if running in src/ directory; use XSCHEM_SHAREDIR shell variable (if defined and directory existing), else set XCSCHEM_SHAREDIR to `pwd` if started from src/ dir, else set compile set XSCHEM_SHAREDIR. xschemrc can override this XSCHEM_SHAREDIR setting. 2025-01-05 01:29:04 +01:00
Makefile.conf.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions