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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
760 Commits 3 Branches 10 Tags 88 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
Roff 2%
Yacc 0.7%
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Stefan Frederik 51e85c2d69 doc updates about menu text change 2021-12-01 15:03:10 +01:00
XSchemWin removed duplicate netlist_dir global var in C code, use tcl netlist_dir variable, some widgets now display on top of current schematic window instead of xschem`s master window (use [xschem get topwindow] instead of ".") 2021-11-23 17:02:36 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
scconfig old_winpath[] removed from globals, put as static string into callback(), fix ngspice::annotate netlist_dir fetching. 2021-11-23 23:20:10 +01:00
src better menu text 2021-12-01 12:42:40 +01:00
tests removed duplicate netlist_dir global var in C code, use tcl netlist_dir variable, some widgets now display on top of current schematic window instead of xschem`s master window (use [xschem get topwindow] instead of ".") 2021-11-23 17:02:36 +01:00
xschem_library added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example 2021-12-01 14:25:27 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in scconfig test for dup2() availability 2021-10-25 01:53:00 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions