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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 507c44e117 speed optimizations in drawbezier() 2024-02-29 04:41:06 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin recognize integrated_noise, improve `xschem preview_window` command 2024-01-27 11:42:05 +01:00
doc added wave processor functions `re()` and `im()` to get real and imaginary part from modulus and phase (expressed in deg) 2024-02-25 23:54:39 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src speed optimizations in drawbezier() 2024-02-29 04:41:06 +01:00
tests update hash for greycnt.sch in xschemtest.tcl 2024-01-04 00:09:28 +01:00
xschem_library call translate(-1, ..) for text objects containing @... and referencing no valid instance (floater=true) so non instance-related @vars are resolved. translate(): resolve @spice_get_voltage(net) without trying to calculated fqnet from net if no valid inst (-1) is given 2024-02-26 16:05:11 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions