A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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stefan schippers 49bed53ba1 tcl_files: do a tcl "subst" on tcl_files before sourcing file items, so xschem commands (like abs_sym_path) can be used		2025-09-23 22:40:05 +02:00
.github/workflows	Update ci.yaml	2025-05-07 16:16:25 +02:00
XSchemWin	print_spice_element(): do not substitute "extra" pins in format string (like @body) with body=xxx given in parent symbol instance attributes	2025-05-20 02:51:52 +02:00
doc	update docs for new bindkeys	2025-09-13 11:06:00 +02:00
scconfig	some fixes for gcc-15 (-std=c23), smaller threshold for click & move that will abort move, added smaller verilog cosim example (tb_counter_wrapper.sch), arbitrary top level names allowed in create_new_window() and switch_window() (no tabbed interface)	2025-09-19 14:18:06 +02:00
src	tcl_files: do a tcl "subst" on tcl_files before sourcing file items, so xschem commands (like abs_sym_path) can be used	2025-09-23 22:40:05 +02:00
tests	vector unnamed nets are set as net%d_[%d..0] instead of net%d[%d:0] so they are compatible with spice and Vacask	2025-08-03 00:15:57 +02:00
xschem_library	improve tb_diff_amp.sch testcase	2025-09-23 08:19:37 +02:00
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AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
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Makefile	make uninstall: remove empty directories (share/xschem and share/doc/xschem); make command `xschem help` work also if running in src/ directory; use XSCHEM_SHAREDIR shell variable (if defined and directory existing), else set XCSCHEM_SHAREDIR to `pwd` if started from src/ dir, else set compile set XSCHEM_SHAREDIR. xschemrc can override this XSCHEM_SHAREDIR setting.	2025-01-05 01:29:04 +01:00
Makefile.conf.in	remove check for libreadline (not used)	2024-11-13 01:35:24 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions