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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 3eeaf53cd4 improve quit_xschem command and xschem new_schematic destroy_all 2023-06-09 08:12:39 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin added command `xschem getprop instance_notcl` to avoid tcl subst of the resulting attribute; improved fix_symbols to fix also parametrized generators (pcells) 2023-06-08 23:02:40 +02:00
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src improve quit_xschem command and xschem new_schematic destroy_all 2023-06-09 08:12:39 +02:00
tests update hash of greycnt.v in xschemtest.tcl due to comments lines added in netlist for bus taps 2023-06-08 11:01:34 +02:00
xschem_library updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol 2023-06-08 01:08:05 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions