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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 3c1603ea5e add wire also if separating component from a running wire (not connected at endpoints) 2022-01-18 02:10:56 +01:00
XSchemWin button press on a tab, hold button and drag onto another tab --> swap tabs 2022-01-12 23:55:46 +01:00
doc left anchor window title in tab buttons 2022-01-13 15:40:20 +01:00
scconfig remove xcb probing in hooks.c 2022-01-17 17:55:27 +01:00
src add wire also if separating component from a running wire (not connected at endpoints) 2022-01-18 02:10:56 +01:00
tests button press on a tab, hold button and drag onto another tab --> swap tabs 2022-01-12 23:44:52 +01:00
xschem_library add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing 2022-01-15 13:31:45 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove xcb probing in hooks.c 2022-01-17 17:55:27 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions