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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Chayan Deb 3b55410709 [Added New Feature]: New menu option 'Enable orthogonal wiring' is now accessible through the 'Options' menu. This option is kept ON-BY-DEFAULT and can be disabled through the menu, 'Shift+L'-keyboard-shortcut, or by editing the 'xschemrc' file to make xschem-editor revert back to it's old behavior - which was drawing wires in free-form mode (Unconstrained move). The functionality of the 'h' and 'v' keys are preserved, and they can still be used to force the editor to only draw horizontal or vertical wires respectively. 2025-01-05 13:20:52 +05:30
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin updated greycnt.sch example 2024-12-18 14:01:50 +01:00
doc add `2` and `3` argument to set_modify (do only clear/set modified flag), save() -> save_schematic(): do not update title/tab names if saving with same name. 2025-01-04 12:24:22 +01:00
scconfig xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
src [Added New Feature]: New menu option 'Enable orthogonal wiring' is now accessible through the 'Options' menu. This option is kept ON-BY-DEFAULT and can be disabled through the menu, 'Shift+L'-keyboard-shortcut, or by editing the 'xschemrc' file to make xschem-editor revert back to it's old behavior - which was drawing wires in free-form mode (Unconstrained move). The functionality of the 'h' and 'v' keys are preserved, and they can still be used to force the editor to only draw horizontal or vertical wires respectively. 2025-01-05 13:20:52 +05:30
tests update xschemtest expected netlist hashes 2024-12-23 11:15:36 +01:00
xschem_library code comments 2024-12-23 12:24:06 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog 2024-12-16 17:01:38 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove check for libreadline (not used) 2024-11-13 01:35:24 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions