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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,872 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
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Stefan Schippers 3b3e723f8f add new command `Shift-M`, move selected instances adding wires when separating overlapping instance pins (Connect by kissing) 2023-06-10 18:57:32 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin added command `xschem getprop instance_notcl` to avoid tcl subst of the resulting attribute; improved fix_symbols to fix also parametrized generators (pcells) 2023-06-08 23:02:40 +02:00
doc add new command `Shift-M`, move selected instances adding wires when separating overlapping instance pins (Connect by kissing) 2023-06-10 18:57:32 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src add new command `Shift-M`, move selected instances adding wires when separating overlapping instance pins (Connect by kissing) 2023-06-10 18:57:32 +02:00
tests update hash of greycnt.v in xschemtest.tcl due to comments lines added in netlist for bus taps 2023-06-08 11:01:34 +02:00
xschem_library updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol 2023-06-08 01:08:05 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update copyright info to 2023 2023-05-21 12:52:19 +02:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions