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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 3a405bbce3 bus_tap.sym: show annotated voltage (remove hidden text attribute) 2024-12-13 14:37:35 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin add ability to read ASCII raw files 2024-11-06 11:59:00 +01:00
doc xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
scconfig xschem raw add: add optional sweep_var parameter 2024-12-09 00:00:27 +01:00
src add verilator in addition to icarus verilog simulator 2024-12-12 12:45:24 +01:00
tests get_additional_symbols(): some sanity checks, descend_schematic() more options in set_title argument (avoid set title, avoid processing pins/nets, avoid descending into i-th xdec[3] instance, descend as a whole xdec[3:0], add `xschem get_additional_symbols what` command, allow `xschem get_sch_from_sym -1 inv.sym` to get schematic associated with symbol. hier_psprint(): avoid printing / listing duplicate schematics, improved traversal.tcl 2024-11-05 13:59:37 +01:00
xschem_library bus_tap.sym: show annotated voltage (remove hidden text attribute) 2024-12-13 14:37:35 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions