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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
140 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
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Stefan Schippers 39cd1a77ed fix a regression in delete(): instance hash was not updated. removed some redundant drawing in copy operations 2020-10-03 04:33:52 +02:00
XSchemWin various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c 2020-10-02 03:21:22 +02:00
doc doc updates 2020-09-30 01:34:18 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src fix a regression in delete(): instance hash was not updated. removed some redundant drawing in copy operations 2020-10-03 04:33:52 +02:00
tests various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c 2020-10-02 03:21:22 +02:00
xschem_library mos_power_ampli.sym and solar_panel.sch examples updated to display symbolnet names on pins 2020-10-02 15:45:30 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog fix Browse button in edit symbol prop dialog 2020-09-15 14:15:43 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE added LICENSE 2020-08-09 09:12:07 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
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README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Add manual link 2020-08-08 16:04:20 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html