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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers 379938fe03 if selection is present when exporting pdf assume it is a bboxed pdf, do not print page title. Fix set_viewport_size setting line width to 1 instead of using current value 2023-12-11 18:28:23 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin fix occasional crashes due to graph_fullxzoom() getting sweep variable index in raw file before switching to graph-specific raw file 2023-11-29 01:26:45 +01:00
doc update docs about new additions to the `xschem print` command 2023-12-11 15:22:36 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src if selection is present when exporting pdf assume it is a bboxed pdf, do not print page title. Fix set_viewport_size setting line width to 1 instead of using current value 2023-12-11 18:28:23 +01:00
tests spice.awk: do not join user code lines 2023-12-03 21:33:03 +01:00
xschem_library better line width calculation / restore in export images 2023-12-11 16:06:49 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog for 3.4.4 2023-10-05 08:06:47 +02:00
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Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in Add description for FIX_BROKEN_TILED_FILL in config.h.in 2023-09-22 01:21:32 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions