A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

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Stefan Schippers 2ffb4f792e according to answer from ngspice guys ngspice does not accept continuation lines for .title, .include and .lib statements, so break.awk will avoid breaking those lines. reversed default for tcl dim_background variable, so toggle colorscheme will work.		2020-10-23 01:19:03 +02:00
XSchemWin	according to answer from ngspice guys ngspice does not accept continuation lines for .title, .include and .lib statements, so break.awk will avoid breaking those lines. reversed default for tcl dim_background variable, so toggle colorscheme will work.	2020-10-23 01:19:03 +02:00
doc	doc updates (developer info)	2020-10-09 03:04:49 +02:00
scconfig	"xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg)	2020-09-22 13:35:55 +02:00
src	according to answer from ngspice guys ngspice does not accept continuation lines for .title, .include and .lib statements, so break.awk will avoid breaking those lines. reversed default for tcl dim_background variable, so toggle colorscheme will work.	2020-10-23 01:19:03 +02:00
tests	better wire connecting bubble zoom scaling at different snap levels	2020-10-07 19:45:40 +02:00
xschem_library	spice netlist postprocessing will not break ".include " lines as ngspice does not like these. make_sch_from_spice.awk adapted to import sky130 standard cells, spice netlister will print extra nodes (inherited connections or pins-by-attribute) in the order specified by the format string, instead of dumping the "extra" attribute after all "real" pins, this allows to mix attribute pins with the other pins.	2020-10-21 18:18:53 +02:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
AUTHORS	populating xschem git repo	2020-08-08 15:47:34 +02:00
COPYING	populating xschem git repo	2020-08-08 15:47:34 +02:00
Changelog	fix Browse button in edit symbol prop dialog	2020-09-15 14:15:43 +02:00
INSTALL	populating xschem git repo	2020-08-08 15:47:34 +02:00
LICENSE	Update LICENSE	2020-10-10 11:44:58 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile.conf.in	populating xschem git repo	2020-08-08 15:47:34 +02:00
README	populating xschem git repo	2020-08-08 15:47:34 +02:00
README.md	Update README.md	2020-10-08 00:54:06 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions