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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
388 Commits 3 Branches 10 Tags 89 MiB
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Tcl 15.7%
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Stefan Frederik 2e18119645 remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes 2020-12-17 18:26:46 +01:00
XSchemWin windows install updates 2020-12-16 10:51:41 +01:00
doc added symbol creation video in documentation 2020-12-14 23:31:04 +01:00
scconfig scconfig updates to detect custom tcl-tk installations (MacOS issue) 2020-12-12 11:02:07 +01:00
src remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes 2020-12-17 18:26:46 +01:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes 2020-12-17 18:26:46 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
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Changelog fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli 2020-12-17 03:48:34 +01:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
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README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md Update README_MacOS.md 2020-12-12 02:18:39 +01:00
config.h.in better comments in config.h.in 2020-10-28 00:23:26 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions