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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
751 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.7%
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Stefan Frederik 1c18211894 use tclgetvar for XSCHEM_TMP_DIR 2021-11-29 18:26:20 +01:00
XSchemWin removed duplicate netlist_dir global var in C code, use tcl netlist_dir variable, some widgets now display on top of current schematic window instead of xschem`s master window (use [xschem get topwindow] instead of ".") 2021-11-23 17:02:36 +01:00
doc avoid quitting the program for some serious but non fatal errors, add some error reporting, some documentation updates (faq.html) 2021-11-29 17:29:09 +01:00
scconfig old_winpath[] removed from globals, put as static string into callback(), fix ngspice::annotate netlist_dir fetching. 2021-11-23 23:20:10 +01:00
src use tclgetvar for XSCHEM_TMP_DIR 2021-11-29 18:26:20 +01:00
tests removed duplicate netlist_dir global var in C code, use tcl netlist_dir variable, some widgets now display on top of current schematic window instead of xschem`s master window (use [xschem get topwindow] instead of ".") 2021-11-23 17:02:36 +01:00
xschem_library Windows does not recognize XPending, fix typo for verilog_format`s port name: g instead of f 2021-11-26 13:16:52 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in scconfig test for dup2() availability 2021-10-25 01:53:00 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions