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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 18da3fe78d doc updates about new expandlabel AAA[0:1:3:4] 2022-10-05 02:30:14 +02:00
XSchemWin (Joanne) update to be clearer on how to compile xschem (from scratch vs using XSchemWin.sln) on Windows using VS2022. font.sch micro edits 2022-09-28 11:33:48 +02:00
doc doc updates about new expandlabel AAA[0:1:3:4] 2022-10-05 02:30:14 +02:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src added label notation EN[0:3:6:5]: EN[start🔚offset:repetitions], it will expand to a 20 bit bus: a[0],a[1],a[2],a[3],a[6],a[7],a[8],a[9],a[12],a[13],a[14],a[15],a[18],a[19],a[20],a[21],a[24],a[25],a[26],a[27] 2022-10-05 02:23:37 +02:00
tests update xschemtest.tcl 2022-10-04 00:39:48 +02:00
xschem_library refactor str_hash_* and int_hash_* functions 2022-10-05 01:18:45 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions