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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,433 Commits 3 Branches 10 Tags 87 MiB
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stefan schippers 17e24e0f5f has_included_subcircuit(): correctly handle bussed ports in symbol and spice .subckt file 2024-01-14 11:28:51 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin set tab/window title if xschem invoked with `xschem -n file.sch`. fix poweramp.sch testbench for Xyce sim. 2024-01-11 08:19:25 +01:00
doc add `hide=instance` attribute for in-symbol text objects (in addition to hide=true or hide=false). If set the text is invisible in instantiated symbols, but is visible if descending into the symbol 2024-01-08 15:47:01 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src has_included_subcircuit(): correctly handle bussed ports in symbol and spice .subckt file 2024-01-14 11:28:51 +01:00
tests update hash for greycnt.sch in xschemtest.tcl 2024-01-04 00:09:28 +01:00
xschem_library has_included_subcircuit(): correctly handle bussed ports in symbol and spice .subckt file 2024-01-14 11:28:51 +01:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
Changelog update Changelog for 3.4.4 2023-10-05 08:06:47 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE update license info 2021-07-27 16:42:54 +02:00
Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in Add description for FIX_BROKEN_TILED_FILL in config.h.in 2023-09-22 01:21:32 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions