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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,083 Commits 3 Branches 10 Tags 88 MiB
C 71.5%
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Awk 8.2%
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Stefan Frederik 15e67e04b7 added missing (src/utile/) utile.bat and utile3.bat 2022-05-06 23:42:00 +02:00
XSchemWin update to VS2022 (Joanne) 2022-04-26 11:43:04 +02:00
doc add "--command" command line option to execute commands after initialization (whereas "--tcl" executes commands before initialization) 2022-05-06 23:19:41 +02:00
scconfig more conversion warnings suppressed 2022-04-28 10:12:16 +02:00
src added missing (src/utile/) utile.bat and utile3.bat 2022-05-06 23:42:00 +02:00
tests update xschemtest.tcl to reflect new verilog 2001 syntax for params 2022-04-25 11:30:23 +02:00
xschem_library regression fix: attempt to write into target netlist even if fopen() failed 2022-05-05 22:42:25 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog bump version to 3.0.0; prepare for 3.0.0 release 2021-09-11 07:53:11 +02:00
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LICENSE update license info 2021-07-27 16:42:54 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions