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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,487 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
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stefan schippers 1336e25e68 added xschem raw_query set node n value [dset] command to change loaded raw data 2024-02-20 17:17:38 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin recognize integrated_noise, improve `xschem preview_window` command 2024-01-27 11:42:05 +01:00
doc added xschem raw_query set node n value [dset] command to change loaded raw data 2024-02-20 17:17:38 +01:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src added xschem raw_query set node n value [dset] command to change loaded raw data 2024-02-20 17:17:38 +01:00
tests update hash for greycnt.sch in xschemtest.tcl 2024-01-04 00:09:28 +01:00
xschem_library added missing xschem_library/inst_sch_select/comp3* files 2024-01-22 15:33:50 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions