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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 0f5881cd61 print_spice_subckt(): check for tcl_hook2() errors, check for NULL in strtoupper/strtolower, fix unitialized local variable 2022-08-23 10:01:32 +02:00
XSchemWin user selectable log X scale instead of assiming log X for AC analyses only 2022-08-05 00:57:03 +02:00
doc sys-lib-path: add /devices in configure log shown text 2022-08-13 11:02:18 +02:00
scconfig instance names (refdes) are hashed as uppercase, so collision check will be case insensitive, if enabled 2022-08-21 10:22:56 +02:00
src print_spice_subckt(): check for tcl_hook2() errors, check for NULL in strtoupper/strtolower, fix unitialized local variable 2022-08-23 10:01:32 +02:00
tests remove extra blank in .subckt spice netlist lines 2022-08-18 12:14:23 +02:00
xschem_library update cmos_example.sch 2022-08-15 10:53:16 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
Changelog Update Changelog 2022-07-28 10:31:07 +02:00
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README update license info 2021-07-27 16:42:54 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions