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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
567 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
Other 1.7%
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Stefan Frederik 03a97df404 correctly redraw schematic at end of hierarchical pdf export (full zoom and draw) 2021-06-21 19:11:36 +02:00
XSchemWin make_sym_lcc.awk: declare "value" as local variable inside process_box_line() to avoid clashes with global "value" 2021-06-05 08:58:38 +02:00
doc removed/updated obsolete keybinding descriptions, removed status check on Delete key events 2021-01-13 13:44:57 +01:00
scconfig make_sym_lcc.awk: declare "value" as local variable inside process_box_line() to avoid clashes with global "value" 2021-06-05 08:58:38 +02:00
src correctly redraw schematic at end of hierarchical pdf export (full zoom and draw) 2021-06-21 19:11:36 +02:00
tests redraw wire/line/rect/arc/poly rubbers after changing zoom/panning; do not wait for Motion events 2020-12-29 03:45:12 +01:00
xschem_library do a tcl evaluation of the "schematic" attribute of a symbol if the attribute is within a tcleval(...) expression. This way tcl variables/expressions can be used to determine the schematic to descend into when traversing/netlisting. example: schematic=tcleval(poweramp_${::mode}.sch). 2021-06-17 00:25:39 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions