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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,887 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
Tcl 15.8%
Awk 8.2%
Roff 2%
Yacc 0.7%
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stefan schippers 01806eaa10 fix meaningless pin attributes on tier.tcl 2023-06-15 09:05:15 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin added command `xschem getprop instance_notcl` to avoid tcl subst of the resulting attribute; improved fix_symbols to fix also parametrized generators (pcells) 2023-06-08 23:02:40 +02:00
doc show red dot when cuting a wire with new alt-right button click on a wire. Added also menu command in Tools 2023-06-14 10:08:50 +02:00
scconfig add "inst_sch_select" example dir in search path in scconfig/hooks.c 2023-05-05 07:59:24 +02:00
src show red dot when cuting a wire with new alt-right button click on a wire. Added also menu command in Tools 2023-06-14 10:08:50 +02:00
tests update spice netlist hash for inst_sch_select.sch in xschemtest.tcl 2023-06-13 23:20:28 +02:00
xschem_library fix meaningless pin attributes on tier.tcl 2023-06-15 09:05:15 +02:00
.gitignore gitignore update 2023-01-16 13:41:16 -07:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
CMakeLists.txt Added png and embedded graphs to ps and pdf export 2023-01-15 21:34:43 -07:00
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Makefile.conf.in added libjpeg detection code, so postscript image embedding will be disabled if libjpeg not present 2023-01-18 03:33:28 +01:00
README update license info 2021-07-27 16:42:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions