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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik 01764bc929 reset globfilter to {*} after using it 2022-01-02 00:05:05 +01:00
XSchemWin fix BadDrawable regression in free_rawfile(): after deleting data a draw() was called, but since this function is called also in exit handler all windows are already closed. Added digital waveforms and bussed signal display 2021-12-29 05:11:39 +01:00
doc doc updates about menu text change 2021-12-01 15:03:10 +01:00
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tests speed optimizations in draw_graph() 2022-01-01 21:47:17 +01:00
xschem_library various fixes in multi trace/multi dataset graphs 2022-01-01 04:22:23 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions