stefan schippers
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af22c256b3
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default to unlocked state (lock=false) at title 1st placement
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2023-01-07 11:34:47 +01:00 |
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stefan schippers
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4c0d5023f5
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allow 0 width lines (faster device dependent implementation) if user defined line width is set (to 0), add devices/title-3.sym
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2023-01-07 11:28:28 +01:00 |
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Stefan Frederik
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28cc187b56
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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Stefan Schippers
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5e98241df1
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NumLock and CapsLock check for windows
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2020-09-22 21:02:51 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |