2 Commits

Author	SHA1	Message	Date
Stefan Frederik	756a7ba06d	swap s/d in verilog netlisting rule for enhancement load "rnmos4.sym" so it can be used as usually done with nmos devices (drain side up) .	2021-12-01 15:53:14 +01:00
Stefan Frederik	dcb37ef295	added devices/rnmos4.sym for enhancement load nmos gate simulation in verilog, updated test_mos_verilog.sch example	2021-12-01 14:25:27 +01:00