3 Commits

Author	SHA1	Message	Date
Stefan Frederik	b7b9d666a9	fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion	2020-12-23 18:16:53 +01:00
Stefan Schippers	f8f1626c1b	cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator)	2020-10-13 02:52:37 +02:00
Stefan SChippers	5e8df730a0	populating xschem git repo	2020-08-08 15:47:34 +02:00