xschem resolved_net command: add [net] parameter; instcheck(): use inst[].lab instead of get_tok_value(inst[].prop_ptr, "lab",0)
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@ -969,9 +969,10 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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Example: xschem replace_symbol R3 capa.sym </pre>
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Example: xschem replace_symbol R3 capa.sym </pre>
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<li><kbd> reset_flags</kbd></li><pre>
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<li><kbd> reset_flags</kbd></li><pre>
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Reset cached instance and symbol cached flags (inst->flags, sym->flags) </pre>
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Reset cached instance and symbol cached flags (inst->flags, sym->flags) </pre>
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<li><kbd> resolved_net</kbd></li><pre>
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<li><kbd> resolved_net [net]</kbd></li><pre>
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returns the topmost full hierarchy name of selected net/pin/label
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if 'net' is given return its topmost full hierarchy name
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nets connected to I/O ports are mapped to upper level recursively </pre>
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else returns the topmost full hierarchy name of selected net/pin/label.
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Nets connected to I/O ports are mapped to upper level recursively</pre>
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<li><kbd> rotate</kbd></li><pre>
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<li><kbd> rotate</kbd></li><pre>
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Rotate selected objects around their centers </pre>
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Rotate selected objects around their centers </pre>
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<li><kbd> save</kbd></li><pre>
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<li><kbd> save</kbd></li><pre>
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@ -874,7 +874,8 @@ static int instcheck(int n, int p)
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const char *tap;
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const char *tap;
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dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[0]);
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dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[0]);
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if(!inst[n].node[1]) { /* still unnamed */
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if(!inst[n].node[1]) { /* still unnamed */
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tap = get_tok_value(inst[n].prop_ptr, "lab", 0);
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/* tap = get_tok_value(inst[n].prop_ptr, "lab", 0); */
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tap = inst[n].lab;
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/* Check if this is a bus slice and must be appended to bus base name */
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/* Check if this is a bus slice and must be appended to bus base name */
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if(tap[0] == '[' || isonlydigit(tap)) {
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if(tap[0] == '[' || isonlydigit(tap)) {
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/* find bus basename, from beginning or first character after ',' and ' ' */
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/* find bus basename, from beginning or first character after ',' and ' ' */
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@ -2928,15 +2928,19 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
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Tcl_ResetResult(interp);
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Tcl_ResetResult(interp);
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}
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}
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/* resolved_net
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/* resolved_net [net]
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* returns the topmost full hierarchy name of selected net/pin/label
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* if 'net' is given return its topmost full hierarchy name
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* nets connected to I/O ports are mapped to upper level recursively */
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* else returns the topmost full hierarchy name of selected net/pin/label.
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* Nets connected to I/O ports are mapped to upper level recursively */
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else if(!strcmp(argv[1], "resolved_net"))
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else if(!strcmp(argv[1], "resolved_net"))
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{
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{
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char *net = NULL, *rn = NULL;
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const char *net = NULL;
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char *rn = NULL;
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Tcl_ResetResult(interp);
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Tcl_ResetResult(interp);
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prepare_netlist_structs(0);
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prepare_netlist_structs(0);
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if(xctx->lastsel == 1) {
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if(argc > 2) {
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net = argv[2];
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} else if(xctx->lastsel == 1) {
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if(xctx->sel_array[0].type == ELEMENT) {
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if(xctx->sel_array[0].type == ELEMENT) {
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int n=xctx->sel_array[0].n;
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int n=xctx->sel_array[0].n;
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if(xctx->inst[n].ptr >= 0) {
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if(xctx->inst[n].ptr >= 0) {
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@ -3418,7 +3418,9 @@ const char *translate(int inst, const char* s)
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++path;
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++path;
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}
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}
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prepare_netlist_structs(0);
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prepare_netlist_structs(0);
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if(pin_prop_ptr) net = get_tok_value(pin_prop_ptr, "lab", 0);
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if(pin_prop_ptr) {
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net = get_tok_value(pin_prop_ptr, "lab", 0);
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}
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if(net == NULL || net[0] == '\0') net = net_name(inst,0, &multip, 0, 0);
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if(net == NULL || net[0] == '\0') net = net_name(inst,0, &multip, 0, 0);
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len = strlen(path) + strlen(net) + 1;
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len = strlen(path) + strlen(net) + 1;
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dbg(1, "translate() @spice_get_voltage: inst=%s\n", xctx->inst[inst].instname);
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dbg(1, "translate() @spice_get_voltage: inst=%s\n", xctx->inst[inst].instname);
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@ -1,4 +1,4 @@
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v {xschem version=3.1.0 file_version=1.2
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v {xschem version=3.4.0 file_version=1.2
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}
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}
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G {}
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G {}
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K {type=subcircuit
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K {type=subcircuit
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@ -51,7 +51,8 @@ dataset=-1}
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P 4 5 560 -700 560 -510 1350 -510 1350 -700 560 -700 {dash=3}
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P 4 5 560 -700 560 -510 1350 -510 1350 -700 560 -700 {dash=3}
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P 4 5 820 -920 820 -730 1350 -730 1350 -920 820 -920 {dash=3}
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P 4 5 820 -920 820 -730 1350 -730 1350 -920 820 -920 {dash=3}
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P 4 5 0 -1160 1840 -1160 1840 0 -0 0 0 -1160 {dash=4}
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P 4 5 0 -1160 1840 -1160 1840 0 -0 0 0 -1160 {dash=4}
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T {These 2 instances are equivalent} 260 -310 0 0 0.4 0.4 {}
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T {These 2 instances
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are equivalent} 260 -310 0 0 0.4 0.4 {}
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T {Example of using a schematic as a component instance
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T {Example of using a schematic as a component instance
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instead of the usual symbol. LCC: Local Custom Cell.
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instead of the usual symbol. LCC: Local Custom Cell.
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@ -84,7 +85,7 @@ lab=ZZ}
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C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3"}
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C {vsource.sym} 50 -140 0 0 {name=V1 value="pwl 0 0 1u 0 5u 3"}
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C {lab_pin.sym} 50 -170 0 0 {name=p4 lab=A}
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C {lab_pin.sym} 50 -170 0 0 {name=p4 lab=A}
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C {lab_pin.sym} 50 -110 0 0 {name=p5 lab=0}
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C {lab_pin.sym} 50 -110 0 0 {name=p5 lab=0}
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C {code_shown.sym} 510 -250 0 0 {name=STIMULI
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C {code_shown.sym} 480 -280 0 0 {name=STIMULI
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only_toplevel=true
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only_toplevel=true
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tclcommand="xschem edit_vi_prop"
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tclcommand="xschem edit_vi_prop"
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value=".control
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value=".control
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