tedax, verilog, spice netlists: do not expand unused subcircuits (due to *_ignore attrs on instances/symbols)

src/spice_netlist.c

@@ -23,6 +23,7 @@
 #include "xschem.h"
 
 static Str_hashtable model_table = {NULL, 0}; /* safe even with multiple schematics */
+static Int_hashtable used_symbols = {NULL, 0};
 
 static const char *hier_psprint_mtime(const char *file_name)
 {
@@ -206,7 +207,10 @@ static int spice_netlist(FILE *fd, int spice_stop )
          fprintf(fd,"**** end user architecture code\n");
        } else {
          const char *m;
-         if(print_spice_element(fd, i)) fprintf(fd, "**** end_element\n");
+         if(print_spice_element(fd, i)) {
+           int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+           fprintf(fd, "**** end_element\n");
+         }
          /* hash device_model attribute if any */
          m = get_tok_value(xctx->inst[i].prop_ptr, "device_model", 0);
          if(m[0]) str_hash_lookup(&model_table, model_name(m), m, XINSERT);
@@ -252,6 +256,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  statusmsg("",2);  /* clear infowindow */
  str_hash_init(&subckt_table, HASHSIZE);
  str_hash_init(&model_table, HASHSIZE);
+ int_hash_init(&used_symbols, HASHSIZE);
  record_global_node(2, NULL, NULL); /* delete list of global nodes */
  bus_char[0] = bus_char[1] = '\0';
  xctx->hiersep[0]='.'; xctx->hiersep[1]='\0';
@@ -410,6 +415,7 @@ int global_spice_netlist(int global)  /* netlister driver */
    get_additional_symbols(1);
    for(i=0;i<xctx->symbols; ++i)
    {
+    if(int_hash_lookup(&used_symbols, xctx->sym[i].name, 0, XLOOKUP) == NULL) continue;
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
@@ -499,6 +505,7 @@ int global_spice_netlist(int global)  /* netlister driver */
  }
  str_hash_free(&model_table);
  str_hash_free(&subckt_table);
+ int_hash_free(&used_symbols);
  if(first) fprintf(fd,"**** end user architecture code\n");
 
 

src/tedax_netlist.c

@@ -21,7 +21,7 @@
  */
 
 #include "xschem.h"
-
+static Int_hashtable used_symbols = {NULL, 0};
 static int tedax_netlist(FILE *fd, int tedax_stop )
 {
   int err = 0;
@@ -66,6 +66,8 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
          fprintf(fd,"#**** end user architecture code\n");
        } else {
          print_tedax_element(fd, i) ;  /* this is the element line  */
+         int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+
        }
      }
     }
@@ -138,6 +140,7 @@ int global_tedax_netlist(int global)  /* netlister driver */
  xctx->push_undo();
  statusmsg("",2);  /* clear infowindow */
  str_hash_init(&subckt_table, HASHSIZE);
+ int_hash_init(&used_symbols, HASHSIZE);
  record_global_node(2, NULL, NULL); /* delete list of global nodes */
  bus_char[0] = bus_char[1] = '\0';
  xctx->hiersep[0]='.'; xctx->hiersep[1]='\0';
@@ -206,6 +209,7 @@ int global_tedax_netlist(int global)  /* netlister driver */
    get_additional_symbols(1);
    for(i=0;i<xctx->symbols; ++i)
    {
+    if(int_hash_lookup(&used_symbols, xctx->sym[i].name, 0, XLOOKUP) == NULL) continue;
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
@@ -245,6 +249,7 @@ int global_tedax_netlist(int global)  /* netlister driver */
  propagate_hilights(1, 0, XINSERT_NOREPLACE);
  draw_hilight_net(1);
  my_free(_ALLOC_ID_, &stored_flags);
+ int_hash_free(&used_symbols);
 
  /* print globals nodes found in netlist 28032003 */
  record_global_node(0,fd,NULL);

src/verilog_netlist.c

@@ -21,6 +21,7 @@
  */
 
 #include "xschem.h"
+static Int_hashtable used_symbols = {NULL, 0};
 
 static int verilog_netlist(FILE *fd , int verilog_stop)
 {
@@ -60,9 +61,15 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
     {
      if(xctx->lastsel)
      {
-      if(xctx->inst[i].sel==SELECTED) print_verilog_element(fd, i) ;
+      if(xctx->inst[i].sel==SELECTED) {
+        print_verilog_element(fd, i) ;
+        int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
+      }
+     }
+     else {
+       print_verilog_element(fd, i) ;  /* this is the element line  */
+       int_hash_lookup(&used_symbols, xctx->inst[i].name, 1, XINSERT); /* symbol is used */
      }
-     else print_verilog_element(fd, i) ;  /* this is the element line  */
     }
    }
    my_free(_ALLOC_ID_, &type);
@@ -98,6 +105,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */
  statusmsg("",2);  /* clear infowindow */
  str_hash_init(&subckt_table, HASHSIZE);
+ int_hash_init(&used_symbols, HASHSIZE);
  xctx->netlist_count=0;
  /* top sch properties used for library use declarations and type definitions */
  /* to be printed before any entity declarations */
@@ -354,6 +362,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
    get_additional_symbols(1);
    for(i=0;i<xctx->symbols; ++i)
    {
+    if(int_hash_lookup(&used_symbols, xctx->sym[i].name, 0, XLOOKUP) == NULL) continue;
     if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
     if(!xctx->sym[i].type) continue;
     my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
@@ -395,6 +404,7 @@ int global_verilog_netlist(int global)  /* netlister driver */
  propagate_hilights(1, 0, XINSERT_NOREPLACE);
  draw_hilight_net(1);
  my_free(_ALLOC_ID_, &stored_flags);
+ int_hash_free(&used_symbols);
 
  dbg(1, "global_verilog_netlist(): starting awk on netlist!\n");
  if(!split_f) {

src/vhdl_netlist.c

@@ -22,7 +22,6 @@
 
 #include "xschem.h"
 
-
 static int vhdl_netlist(FILE *fd , int vhdl_stop)
 {
  int err = 0;
@@ -99,10 +98,10 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
      if(xctx->lastsel)
      {
       if(xctx->inst[i].sel==SELECTED) {
-        print_vhdl_element(fd, i) ;
+        print_vhdl_element(fd, i);
       }
      } else {
-        print_vhdl_element(fd, i) ;
+        print_vhdl_element(fd, i);
      }
     }
    }