reverted examples to verify split mode netlist

2020-12-04 13:14:20 +01:00 · 2020-12-04 13:14:20 +01:00 · d4c289aded
parent c3aad2fbfc
commit d4c289aded
1 changed files with 1 additions and 2 deletions
--- a/xschem_library/examples/mos_power_ampli.sym
+++ b/xschem_library/examples/mos_power_ampli.sym
@ -4,8 +4,7 @@ K {type=subcircuit
 format="@name @pinlist @symname"
 template="name=x1"
 net_name=true
-verilog_netlist=true
-schematic=bus_keeper.sch}
+}
 V {}
 S {}
 E {}