From d4c289aded2c4e44d826ffec665cd29ed3f339cd Mon Sep 17 00:00:00 2001
From: Stefan Frederik <stefan.schippers@gmail.com>
Date: Fri, 4 Dec 2020 13:14:20 +0100
Subject: [PATCH] reverted examples to verify split mode netlist

---
 xschem_library/examples/mos_power_ampli.sym | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/xschem_library/examples/mos_power_ampli.sym b/xschem_library/examples/mos_power_ampli.sym
index 805b91dc..15ba0f00 100644
--- a/xschem_library/examples/mos_power_ampli.sym
+++ b/xschem_library/examples/mos_power_ampli.sym
@@ -4,8 +4,7 @@ K {type=subcircuit
 format="@name @pinlist @symname"
 template="name=x1"
 net_name=true
-verilog_netlist=true
-schematic=bus_keeper.sch}
+}
 V {}
 S {}
 E {}