generic_type defines the type of parameters passed to VHDL components. Consider the following +
generic_type defines the type of parameters passed to VHDL/Verilog components. Consider the following MOS symbol definition; the model attribute is declared as string and it will be quoted in VHDL netlists.
@@ -264,8 +264,7 @@ verilog_stop=true x2 G_y G_a G_b G_c VCC VSS lvnand3 wn=1.8u ln=0.18u wp=1u lp=0.18u m=1 **.ends * expanding symbol: customlogicLib/lvnand3 # of pins=4 -.subckt lvnand3 y a b c VCCPIN VSSPIN -wn=30u ln=2.4u wp=20u lp=2.4u +.subckt lvnand3 y a b c VCCPIN VSSPIN wn=30u ln=2.4u wp=20u lp=2.4u *.opin y *.ipin a *.ipin b @@ -295,9 +294,7 @@ x2 G_y G_a G_b G_c VCC VSS lvnand3 wn=1.8u ln=0.18u wp=1u lp=0.18u m=1 * expanding symbol: customlogicLib/lvnand3 # of pins=4 -.subckt lvnand3 y a b c -wn=30u ln=2.4u wp=20u lp=2.4u -VCCPIN=VCC VSSPIN=VSS +.subckt lvnand3 y a b c wn=30u ln=2.4u wp=20u lp=2.4u VCCPIN=VCC VSSPIN=VSS *.opin y *.ipin a *.ipin b @@ -316,7 +313,24 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1 .ends- as you can see the VSSPIN and VCCPIN are listed as parameters and not as pins in the netlist. + as you can see the VSSPIN and VCCPIN are listed as parameters in addition as pins in the netlist. +
++ This attribute is similar to the extra attribute and is used for verilog netlist. Nodes + listed in this atrribute value will be used as additional pin connections. +
++ the extra attribute is still used in verilog netlist as a list of attributes NOT to pass as + symbol parameters +
++ You may assign the following attributes to an instance: name=X1 VPWR=VCC VGND=GND subckt=NOR2_1 + and you want to have VCC and GND connections to the symbol in the Verilog netlist but do not want + any of these attributes to be + passed as symbol parameters. In this case you set: verilog_extra="VPWR VGND" and + extra="VPWR VGND subckt" since subckt is probably a spice attribute and you don't + want it in verilog.
diff --git a/src/save.c b/src/save.c
index 3eba6d92..62ebd385 100644
--- a/src/save.c
+++ b/src/save.c
@@ -395,6 +395,13 @@ static int read_dataset(FILE *fd, const char *type)
else if(!strncmp(line, "No. Variables:", 14)) {
n = sscanf(line, "No. Variables: %d", &nvars);
dbg(dbglev, "read_dataset(): nvars=%d\n", nvars);
+
+ if(xctx->graph_datasets > 0 && xctx->graph_nvars != nvars) {
+ dbg(0, "Xschem requires all datasets to be saved with identical and same number of variables\n");
+ dbg(0, "There is a mismatch, so this and following datasets will not be read\n");
+ return 1;
+ }
+
if(ac) nvars <<= 1;
if(n < 1) {
dbg(0, "read_dataset(): WAARNING: malformed raw file, aborting\n");
diff --git a/src/spice_netlist.c b/src/spice_netlist.c
index 03e6497a..a57ca956 100644
--- a/src/spice_netlist.c
+++ b/src/spice_netlist.c
@@ -507,11 +507,11 @@ void spice_block_netlist(FILE *fd, int i)
fprintf(fd, "%s\n", sym_def);
} else {
fprintf(fd, "** sch_path: %s\n", filename);
- fprintf(fd, ".subckt %s",skip_dir(xctx->sym[i].name));
- print_spice_subckt(fd, i);
+ fprintf(fd, ".subckt %s ",skip_dir(xctx->sym[i].name));
+ print_spice_subckt_nodes(fd, i);
my_strdup(387, &extra, get_tok_value(xctx->sym[i].prop_ptr,"extra",0) );
- /* this is now done in print_spice_subckt */
+ /* this is now done in print_spice_subckt_nodes */
/*
* fprintf(fd, "%s ", extra ? extra : "" );
*/
diff --git a/src/token.c b/src/token.c
index 983170a0..fb9c25ba 100644
--- a/src/token.c
+++ b/src/token.c
@@ -1561,7 +1561,7 @@ void print_tedax_subckt(FILE *fd, int symbol)
}
-void print_spice_subckt(FILE *fd, int symbol)
+void print_spice_subckt_nodes(FILE *fd, int symbol)
{
int i=0, multip;
const char *str_ptr=NULL;
@@ -1647,7 +1647,7 @@ void print_spice_subckt(FILE *fd, int symbol)
if(!strcmp(get_tok_value(prop, "name",0), token + 2)) break;
}
if(i